On the road to tiny transistors, how flat is flat?
Transistors are the building blocks of modern electronics, used in everything from televisions to laptops. As transistors have become smaller and more compact, so have electronics, which is why your cell phone is a super-powerful computer that fits in the palm of your hand.
But there is a scaling problem: the transistors are now so small that they are difficult to turn off. A key part of the device is the channel that charge carriers (such as electrons) pass through between the electrodes. If this channel becomes too short, quantum effects allow electrons to effectively hop from side to side even when they shouldn’t.
One way to get around this sizing hurdle is to use layers of 2D materials – which are only a single atom thick – as a channel. Atomically thin channels can help turn on even smaller transistors by making it harder for electrons to jump between electrodes. A well-known example of a 2D material is graphene, whose discoverers won the Nobel Prize in Physics in 2010. But there are other 2D materials, and many believe they are the future of transistors, with the promise of reduce the channel thickness from its current 3D limit of a few nanometers (nm, billionths of a meter) to less than a nanometer thick.
Although research has exploded in this area, one problem has been consistently overlooked, according to a team of scientists from the National Institute of Standards and Technology (NIST), Purdue University, Duke University and the University of state of North Carolina. 2D materials and their interfaces – which researchers intend to be flat when stacked on top of each other – may not actually be flat. This non-flatness can in turn significantly affect the performance of the device, sometimes in a good way and sometimes in a bad way.
In a new study published in the April 26, 2022 issue of ACS Nano, the research team reports the results of their measurements of the flatness of these interfaces in transistor devices that incorporate 2D materials. They are the first group to take high resolution microscopy images showing the flatness of these 2D layers in complete device arrays, at a relatively large scale – around 12 micrometers (millionths of a meter) as opposed to 10nm to 100nm more currents. nm range
Scientists have successfully imaged a range of 2D-2D and 2D-3D interfaces in devices they have created using a variety of common fabrication methods. Their results show that assuming interfaces are flat when they are not is a much bigger problem than researchers in the field might have thought.
“We’re enlightening the community on an issue that has been overlooked,” said NIST’s Curt Richter. “This hinders the adoption of new materials. The first step to solving the problem is to know that you have a problem.
Potential benefits include giving the scientific community more control over the manufacture of their devices.
“A lack of understanding of 2D interface flatness is a major barrier to improving devices based on 2D materials,” said lead author Zhihui Cheng, of NIST and Purdue University at the time of this post. the publication. “We have developed a method to quantify flatness at angstrom resolution. This opens many windows for people to explore stress and interactions at 2D interfaces. »
Not as flat as you think
In a traditional transistor, a 3D source electrode releases electrons through a 3D channel to a 3D drain electrode. In 2D transistors, electrons flow through a 2D material. The areas where these different materials meet are called interfaces.
A lack of flatness at these interfaces can cause current flow problems in devices using 2D materials. For example, if there is intimate physical contact between the source metal and the 2D channel, there will also be intimate electrical contact and current will flow smoothly. Conversely, gaps between the 2D channel material and the source compromise electrical contact, reducing current flow. (See the “Idealized vs. Reality” diagram.)
In their paper, the researchers explore several types of 2D interfaces, including those made between the nickel source and drain electrodes, a 2D channel fabricated from the 2D crystal molybdenum disulfide (MoS2), an encapsulation layer of hexagonal boron nitride (hBN) crystal and aluminum oxide.
Scientists typically place 2D and 3D materials on top of each other during the device manufacturing process. For example, researchers sometimes stack 2D materials on pre-configured metal contacts. But the research team found that this type of stacking of 2D materials had a profound effect on their flatness, especially near the contact region. Adding hBN caused the MoS2 deform up to 10 nm on one side of the contact. Areas farther from the contacts tended to be relatively flat, although some of these areas still had a 2-3nm gap.
By testing the effects of atomic layer deposition (a common technique used to deposit a thin layer of material) on the flatness of the 2D interface, the research team found that a direct interface between aluminum oxide and the MoS2 is more distorted than the interfaces between hBN and MoS2. While studying the flatness of the 3D-2D contact interface, the team discovered surprisingly large nanocavities forming in the interface between the nickel contacts and the 2D MoS2 channel.
To relate these non-flat interfaces to real-world concerns about device performance, the team tested the electrical characteristics of a transistor made from these materials. The researchers found that the added non-planarity in the channel actually improved the performance of the device.
“Overall, these results reveal how much the structure of 2D-2D and 2D-3D interfaces depends on the materials as well as the manufacturing process,” Cheng said.
To make their observations, the group used a type of high-resolution scanning transmission electron microscopy (scanning TEM), which can resolve the images to the level of single atoms.
“A lot of this field is pure research,” Richter said. “People make a device or maybe two, and they don’t have extras that they can give a microscopist to take it apart.” In this study, on the other hand, the challenge was to manufacture the devices and then analyze them.
“We didn’t do anything special with the measurements,” Richter continued. “But the combination of electrical measurement know-how and high-resolution TEM expertise – that’s not a common thing.”
“With sub-angstrom resolution and record length in cross-sectional TEM, as well as correlation with device characteristics, our work has broadened and deepened insights into the intricacy and intricacy of 2D interfaces” , Cheng said.
With benefits for all
Applications of the work include reducing unintended device-to-device variation, of which 2D flatness is an important contributing factor, the researchers said.
The imaging method could also help give scientists more control over manufacturing. Some processes introduce mechanical stresses into 2D structures, twisting them like a wrung-out washcloth or crushing and stretching them like an accordion. This can change a device’s performance in unpredictable ways that scientists don’t yet fully understand. A better understanding of how stress affects device performance can give researchers more control over that performance.
“Tension isn’t always a bad thing,” Richter said. “The high-end transistors that people make today actually have a built-in constraint to make them work better. With 2D materials, it’s not as obvious how to do this, but it may be possible to use non-planarity to create the desired deformation.
The authors hope that their work will inspire further efforts to increase the resolution of flatness measurements for 2D interfaces, even at sub-angstrom resolution.
“We have preliminary data, but this is really just the beginning of this investigation,” Cheng said.
—Reported and written by Jennifer Lauren Lee
Article: Z. Cheng, H. Zhang, ST Le, H. Abuzaid, G. Li, L. Cao, AV Davydov, AD Franklin and CA Richter. Are 2D interfaces really flat? ACS Nano. Published in the April 26, 2022 issue. DOI: 10.1021/acsnano.1c11493